Trench gated power device fabrication by doping side walls of partially filled trench

ABSTRACT

A trench is formed in a semiconductor substrate using a mask. The trench is filled with electrode material, a part of which is removed; alternatively, the trench is partially filled with the electrode material. The side walls of the trench are doped with the mask still in place. After the side walls are doped, the remainder of the trench is filled. The result is a trench gated power device such as a MOSFET, MESFET or IGBT.

FIELD OF THE INVENTION

The present invention relates to a method of forming a doped trench aspart of the fabrication of a semiconductor device.

DESCRIPTION OF RELATED ART

A first conventional method of forming a doped trench is to implant asemiconductor with a suitable dopant and then etching through theimplanted region to leave a trench with two side lobes. This methodresults in a doping profile as shown in the graph of FIG. 13. It can beseen from FIG. 13 that this doping method is characterised by a gradualdrop off in concentration in both directions. This method has thedisadvantage that the bottom of the doped region generally will notalign with the electrode material which is added to the trench at alater stage.

U.S. Pat. 4,415,371 describes a second conventional method offabricating a sub-micron dimension NPN lateral transistor. An array ofhundreds of devices may be simultaneously processed on a chip tosub-micron dimensions by establishing tiny active regions for eachtransistor surrounded by field oxide field trenches which are utilizedto dope the substrate within the action region. n+ regions are implantedin the trench by ion implanting at a large angle. The angle of the ionbeams relative to the trench direction ensures that the n+ implantingdoes not extend to the full depth of the trench. This is due to ashadowing effect.

A disadvantage of this device is that the large ion implanting angle(which is necessary to ensure that the trenches are not fully doped) isnon-standard and expensive, and also ionic reflections will reduce theeffectiveness of the shadowing. Also the doped region will generally notalign with the top of the electrode material which is deposited at alater stage.

SUMMARY OF THE INVENTION

In accordance with the present invention we provide a method of forminga doped trench as part of the fabrication of a semiconductor device, themethod comprising:

(i) forming a trench in a semiconductor substrate using a mask to definethe trench region;

(ii) either

a) filling the trench and removing part of the contents of the trench toleave a partially filled trench; or

b) partially filling the trench; and

(iii) doping the side walls of the trench with the mask still in place.

The trench may be filled in step (ii) with any suitable material,depending on the particular type of semiconductor device beingfabricated. Typically the trench is filled with a suitable electrodematerial or combination of materials as in a silicided gate.

The trench may be fully or partially filled with electrode material instep (ii) a), and then removed down to a desired level in the trench eg.by etching. Alternatively the trench may be partially filled in one step(ii) b) up to the desired level. In this case the trench is typicallypartially filled by evaporation of eg. aluminium.

The lateral spread of the doping profile can be accurately controlledand can be made to be very narrow. This is highly advantageous wheretrenches must be placed adjacent and as close as possible to one anotherand allows a particularly high device density. Conventional transistorarrays exhibit a device density of the order of 4 million devices persquare inch. The present invention can be utilised to form a transistorarray with approximately 400 million devices per square inch.

Device parameters such as the particular electrode material used and thedopant ions/atoms will depend on the particular device being fabricated.Typically the electrode is polysilicon or any refractory metal.Typically the dopant atoms are arsenic, phosphorous, boron or antimonyfor silicon, but other elements will be used for other substratematerials.

Preferably the trench is partially filled before the doping step. Thisensures that the bottom of the doping profile is self-aligned to the topof the trench filling material (trench refill). Where the trench refillacts as an electrode in the final device, this will help to minimise thecapacitance between this electrode and the doping region, and ensureschannel continuity in a MOS gated device.

Where the gate is principally polysilicon, the doping step (iii) willalso dope the polysilicon. This will enhance the electrode conductivityand therefore its switching speed.

Typically (as in a MOSFET but not in a device such as a MESFET) adielectric (such as silicon dioxide) will be formed on the surface ofthe trench between steps (i) and (ii). After step (ii) the dielectric atthe upper part of the trench will be exposed. The doping step may thenbe carried out by penetrating through this layer or alternatively, theexposed dielectric material may be removed beforehand.

Typically, the doping step (iii) comprises introducing dopant ions froman angled ionic source. This can result in very high surface dopantconcentrations. This allows very low sheet resistivity regions to beformed. Further, the use of ion implantation means that a rapid thermalanneal can be used which will mean that if the semiconductor device is apower device which is used in a smart power device (where there areother impurity profiles in logic circuits) then this process will bemore suitable as it will not affect the previous processing.

The angled implanting step may be carried out with a low angle ofimplant. This generally means that more than one implanting step couldbe required to dope all sides of the trench. Alternatively the angle ofthe ionic source to the surface of the substrate may be increased. Theresulting ionic reflections from the side walls of the trench thencauses substantially all sides of the trench to be at least partiallydoped and generally only one implanting step could be required.

Alternatively, the doping step (iii) may comprise diffusing dopant ionsinto the sidewalls of the trench from a dopant gas such as arsenic,phosphorous, boron, antimony or any other suitable dopant gas.

Further alternatives for the doping step (iii) include deposition of adopant source such as heavily doped glass; and filling the exposed partof the trench with spin on dopant. Where the dopant mechanism is from adielectric source (such as spin on glass or doped silicon dioxide), thematerial can be conveniently etched back to planarise the trench.

The resulting doped trench can then be utilised in the production of awide variety of semiconductor devices. Examples of such devices are atrench gated power device such as a power MOSFET, MESFET or a powerIGBT, a logic transistor or a memory cell.

The mask which is used to define the trench etch is also used to definethe doping area in step (iii). This allows the doping step to be carriedout by a variety of techniques such as ion implantation or gaseousdiffusion, and any choice of doping (impurity) atoms. A furtheradvantage of using the mask in both steps is that in the field areas(i.e. areas that do not have n+ source regions and where the gatecontact will be made) this mask is desirable as it reduces the gatecapacitance.

The present invention also extends to a device which has beenconstructed according to the previously described method. The devicetypically includes doped regions of the side walls of the trench whichhave a doping concentration which is substantially uniform in theexposed part of the trench (i.e. the part which is not masked byelectrode material after step (ii)). The doped region also typically hasa well defined drop-off in concentration at the top of the electrodematerial.

BRIEF DESCRIPTION OF THE DRAWINGS

A number of embodiments of the invention will now be described withreference to the accompanying figures, in which:

FIG. 1 is a cross-section of a masked substrate prepared for trenchetch;

FIG. 2 is a cross-section of the masked substrate of FIG. 1 after trenchetching;

FIG. 3 is a cross-section of the device of FIG. 2 after trench refill,etch back and oxidation;

FIG. 3A is a cross-section illustrating an alternative method ofpartially filling the trench;

FIG. 4 is a cross-section of a first doping technique comprising angledimplant directly through a thin surface layer;

FIG. 5 is a cross-section of a second doping technique comprising angledimplant directly into the trench wall;

FIG. 6 is a cross-section of a third doping technique with large angleimplant;

FIG. 7 is a cross-section of a fourth doping technique using a diffusionprocess;

FIG. 8 is a cross-section of a fifth doping technique using a soliddopant source;

FIG. 9 is a cross-section of a sixth doping technique using spin-ondopant;

FIG. 10 is a cross-section of a power MOSFET device constructedaccording to the invention;

FIG. 11 is a cross-section of a power IGBT device constructed accordingto the invention;

FIG. 12 is a cross-section of a logic transistor or memory cellconstructed according to the invention;

FIG. 13 is a graph illustrating the doping profile for a conventionalnon-lateral doped region; and,

FIG. 14 is a graph illustrating the doping profile of a laterally dopedregion according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Three stages in the doping preparation process are shown in FIGS. 1-3.Starting with a substrate 1 (typically silicon), a mask 2 is used todefine areas where trenches will be formed (FIG. 1). Depending on thetrench etch chemistry, the mask 2 could be composed of one of a numberof materials such as photoresist, silicon dioxide or silicon nitride.

The trench 3 (FIG. 2) is then etched into the substrate 1 to a depthrelevant to the device design. The trench can be etched using a plasma,ion beam, wet, or similar etch technique.

Once the trench has been etched, the next processing steps are dictatedby the particular device itself. The doping technique described isapplicable to a number of devices, mainly transistors, and it istherefore likely that the next step would be a gate oxidation of thesurface of the trench to leave a layer of oxide 4 (FIG. 3), followed bythe deposition of some kind of gate material 5, e.g. polysilicon, or anyrefractory metal.

This deposition may then be followed by an etch stage to leave thetrench in the half filled state shown in FIG. 3. Alternatively thetrench may be partially filled in one step as illustrated in FIG. 3A,and described below:

(i) The trench 3 is formed as described above but uses a 2 layer mask ofsilicon nitride 30 and silicon dioxide 31 (siO₂).

(ii) Aluminium 32 is then evaporated into the sample and falls much likesnow—giving a “line of sight” covering i.e. not conformal.

(iii) When the sample is placed in a wet solution capable of removingthe SiO₂, the SiO₂ layer 31 is removed, along with all of the aluminiumon the top of it. This is generally known as a “lift off” process. Thenitride layer (still necessary as a doping mask) is left along with thealuminium at the bottom of the trench.

Typically the gate oxide is created by placing the substrate in afurnace with an atmosphere of oxygen, sometimes mixed with steam,nitrogen or hydrogen chloride. The furnace is typically operated at atemperature of 1000 degrees centigrade and cleanliness is a priority asany contaminants can ruin the electrical properties of the oxide.

This is termed “thermal oxidation” and is the standard technique forcreating oxides with good electrical properties (ie. gate dielectricsand not passivation layers such as at the top of the trench). Oxides forother purposes ie. coating and insulating are generally deposited andtherefore have poorer electrical properties. The dry method of thermallyoxidising yields a better oxide (necessary for the accurate control ofturn on voltages and reliability) but is a slower process than wetoxidising (ie. using an atmosphere of oxygen and steam).

Depending on the method of doping taken, this may complete thepreparation for the doping step. If the first doping method is used(FIG. 4) no further action need take place. However, all of the otherprocesses will be much more effective if the substrate is exposed,probably with an etch process to remove the exposed portion of the oxidelayer 4 (ie. above the top of the electrode 5).

The particular doping method chosen will depend on the device type andits specifications.

Six possible doping methods will now be described with reference toFIGS. 4 to 9.

Referring to the first doping method shown in FIG. 4, the lateral dopedregions 8 can be implanted directly through the oxide (or other thinlayers) into the trench walls by dopant ions 6,7 from an angled,isotropic or divergent source. This has the advantage of having a verynarrow lateral spread and removes the need to etch the trench sidewall.However, it is likely that at least two implants will be needed, one foreach side of the trench (at the two angles illustrated by ion beams 6and 7).

In the second doping method shown in FIG. 5, an angled implant 6,7 isagain used to inject dopant directly into the trench wall. However, inthis case the oxide layer 4 has been removed with an etch (ie. the oxidein the exposed region above the electrode 5 has been removed). As aresult lateral profile spreading is much easier to control and predict.

If a large angle implant is used (as illustrated by the ion beams 9 inFIG. 6), it is possible to take advantage of ionic reflections 10 todope both sides of the trench in one step. This has the advantage ofreducing the number of implant steps, but has the followingdisadvantages;

1) doping profiles will probably not be symmetric and,

2) large angle implants are not industry standard and will incur addedexpense.

Profile matching can be optimized by adjusting the mask layer thicknessand the implant angle. The dopant ions could be arsenic, phosphorous,boron or antimony. The substrate crystal orientation will also have aneffect on the ionic reflections.

After the doping steps shown in FIGS. 4-6, a rapid anneal is carriedout.

Dopant atoms can be diffused into the trench sidewalls from a carriergas 11 such as Arsine, Diborane or Phosphine (FIG. 7). This has theadvantage of being a cheap process but may exhibit lower surfaceconcentrations than implanted profiles, with a consequently lowerconductance of the doped regions. The diffusion process is carried outat approximately 1000 degrees centigrade and therefore no separateannealing step is necessary.

The deposition of a dopant source 12 (such as a heavily doped glass e.g.BPSG or PSG or oxide doped with phosphorous or arsenic) allows the easydiffusion of the dopant into the trench sidewalls (FIG. 8). This has theadvantage of being cheap and also the dopant source may be etched backto planarise the trench. Doping is followed by a rapid thermal anneal.

Alternatively, a spin on dopant 13 (such as glass doped with arsenic)can be used (FIG. 9). This has the advantage of not only providing agood source of dopant, but also is an excellent method of planarizingthe trench which will be necessary in many applications. The doping stepis followed by an anneal. This method automatically fills the trenchwith oxide.

FIGS. 1-9 have illustrated a number of initial steps in the fabricationof a device. The method of finishing the device will depend entirely onthe application. Two possible areas of application are discussed belowwith reference to FIGS. 10-12.

Trench Gated Power Devices

These are vertical devices which are all connected in parallel to allowlarge current conduction. Such devices can be capable of withstandingthousands of volts and conducting hundreds of amps. Examples of suchdevices are power MOSFETs (Metal Oxide Semiconductor Field EffectTransistors), MESFETs (Metal Semiconductor Field Effect Transistors) andIGBTs (Insulated Gate Bipolar Transistors.

Two examples are shown in FIGS. 10 and 11. FIG. 10 shows a power MOSFETdevice and FIG. 11 shows a power IGBT. Both trenches are formed on asubstrate with a heavily doped lower layer 14, (n+++ in the case of theMOSFET and p+++ in the case of the IGBT), with an n− drain drift region15 and a p base region 16. The doped lateral regions 8 are n++ sourceregions. In the case of the power MOSFET (FIG. 10) the trench is filledwith an oxide 17, the electrode 18 acts as a source, electrode 19 actsas a drain and the trench electrode 5 acts as a gate. In the case of theIGBT (FIG. 11), the upper electrode 20 acts an emitter and the lowerelectrode 21 acts as a collector. In both cases, the polysilicon layer 5acts as a gate.

Logic Transistors and Memory Cells

FIG. 12 illustrates a logic transistor or memory cell which has beenformed from the trench device previously described in FIGS. 1 to 9. Thetrench is formed in a substrate comprising a p base region 22. Thelaterally doped regions 23,24 are n+ regions. An oxide layer 25 isformed in the upper region of the trench. A passivation layer 26 isformed above the oxide layer. Source 27 and drain 28 electrodes are alsoprovided. Trench electrode 29 acts as a gate.

For better operation, the trench in this device may well penetrate intoa highly conductive epitaxial layer.

All of the above devices can have the p regions swapped for n, andvice-versa for different operating characteristics.

FIG. 13 illustrates the gradual drop off in doping concentrationexhibited by a vertical implant (i.e. the first conventional methoddiscussed earlier). Note the gradual vertical drop off in concentration,indicated at 30.

FIG. 14 illustrates the more uniform doping concentration in the exposedarea of the trench during the implant of the present invention. Notethat the trench surface concentration, indicated at 31, is uniform,unlike in a conventionally doped region illustrated in FIG. 13. Theshadowing technique (i.e. the second conventional technique describedearlier) may yield a similar profile, although there would be asignificant amount of dopant material in areas which would be masked off(particularly by the material 5) during the implant of the presentinvention.

What is claimed is:
 1. A method of fabricating a trench gated powerdevice, the method comprising: (i) forming a trench in a semiconductorsubstrate using a mask to define the trench region; (ii) either a)filling the trench with electrode material and removing part of thecontents of the trench to leave a partially filled trench; or b)partially filling the trench with electrode material; (iii) doping theside walls of the partially filled trench with the mask still in place;and (iv) filling the remainder of the trench after step (iii); whereinthe trench gated power device is one selected from the group consistingof a MOSFET, MESFET and IGBT.
 2. A method according to claim 1 furthercomprising forming a layer of dielectric on the surface of the trenchbetween steps (i) and (ii).
 3. A method according to claim 2, whereinstep (iii) is carried out through the dielectric layer.
 4. A methodaccording to claim 2, further comprising removing the layer ofdielectric from the exposed part of the trench after step (ii).
 5. Amethod according to claim 1, wherein step (iii) comprises implantingdopant ions from an angled ionic source.
 6. A method according to claim5, wherein the angle of the ionic source to the surface of the substrateis large enough such that ionic reflections from the side walls of thetrench causes substantially all sides of the trench to be at leastpartially doped in one implanting step.
 7. A method according to claim1, wherein step (iii) comprises diffusing dopant ions into the sidewallsof the trench from a dopant gas.
 8. A method according to claim 1,wherein step (iii) comprises implanting dopant ions from an isotropicsource.
 9. A method according to claim 1, wherein step (iv) comprisesfilling the trench with oxide.
 10. A method according to claim 1,wherein: the semiconductor substrate comprises: a doped lower layerselected from the group consisting of an n+++ doped lower layer and ap+++ doped lower layer; an n− drain drift region disposed on the dopedlower layer; and a p base region disposed on the n− drain drift region;and step (i) comprises forming the trench in the p base region.